Semiconductor Process
Semiconductor Process
Here is an overview of the processes available at ASE.
Supports the process of the desired size from 2inch wafer to 12inch wafer.
Process alignment with contact aligner using ArF lithography equipment.
Supports CMP process to optimize flatness of any pattern through slurry optimization. (CMP optimization especially in MEMS or NEMS processes.)
Supports wafer bonding and edge trimming process.
Contact aligner, Stepper, E-beam, Nanoimprint etc.
2"~12" Various process capability depends on pattern resolution.
Dry etching(RIE, ICP), Wet etching, lift-off etc.
2"~8" Various process capability depends on pattern resolution. 2"~8" Various process capability depends on pattern resolution.
Various CMP(Metals, Insulations, Substrates), Various grinding(Substrates).
~12" Optimized process proposal from slurry composition level and prebonding surface control for CMOS image sensor, RF device, various MEMS and 3D integrated devices etc.
Low temp plasma bonding(Fusionbonding), Room Temp bonding (Surface activation bonding), Eutectic bonding(Solderbonding), Metaldiffusti on bonding, Glassfrit bonding, Adhesive bonding.
2"~12" Various bonding methods are capable and meet with the needs of room temperature bonding.
Sputtering, Evaporation, CVD, ALD, Electroplating etc.
2"~12" Over 120 kinds of on hand target at sputtering.
Ion implantation, Dicing, Back Grinding, Edge Trimming etc.